1. Field of the Invention
The present invention relates to high-voltage devices and, more particularly, to a semiconductor high-voltage metal-oxide-semiconductor (HVMOS) device and method of manufacturing the same.
2. Description of the Prior Art
Integrated circuits (ICs) containing both high-voltage and low-voltage devices such as high/low voltage MOS transistor devices are known in the art. For example, the low-voltage device may be used in the control circuits as the high-voltage device may be used in electrically programmable read only memory (EPROM) or the driving circuits of the liquid crystal display. Isolation structures such as field oxide layers, which increase the distance between the gate and the source/drain and further decrease the transverse electric field in the channel, are used for preventing short channel effects of the high-voltage MOS device. Thus, the high-voltage MOS transistor devices can function during high-voltage (30V˜40V) operations.
Please refer to FIG. 1 to FIG. 9, wherein FIG. 1 to FIG. 7 are schematic, cross-sectional diagrams illustrating the process steps of fabricating the high-voltage MOS device according to the prior art method; FIG. 8 and FIG. 9 are plan views of the high voltage MOS device at different stages; FIG. 1 is the cross-sectional view taken along line I-I of FIG. 8; and FIG. 3 is the cross-sectional view taken along line II-II of FIG. 9.
As shown in FIG. 1 and briefly referring to FIG. 8, a semiconductor substrate 10 is provided. The semiconductor substrate 10 has thereon a P well 12. Within the P well 12, two spaced apart N wells 14 are formed. A pad oxide layer 16 is then formed over the semiconductor substrate 10. After the formation of the pad oxide layer 16, a mask pattern 20a and mask pattern 20b are formed on the pad oxide layer 16 using conventional lithography and etching processes. The mask pattern 20a defines a channel region of the high-voltage MOS device, while the mask pattern 20b defines source/drain regions of the high-voltage MOS device. The mask patterns 20a and 20b may be made of silicon nitride.
As shown in FIG. 2, a patterned photoresist layer 22 is formed on the semiconductor substrate 10. The patterned photoresist layer 22 has an opening 23 that exposes a pre-selected surface area between the mask pattern 20a and mask pattern 20b. Subsequently, an ion implantation process is carried out to implant N type ion species such as phosphorus or arsenic into the semiconductor substrate 10, thereby forming N drift regions 24 next to the mask pattern 20a. After this, the photoresist layer 22 is stripped off.
As shown in FIG. 3 and briefly referring to FIG. 9, a patterned photoresist layer 32 is formed on the semiconductor substrate 10. The patterned photoresist layer 32 has an opening 33 that exposes a strip of peripheral area in which a P type device isolation diffusion is to be formed. As can be best seen in FIG. 9, the strip of opening 33 bends inward and connects to both ends of the mask pattern 20a that defines the channel region of the high-voltage MOS device. Subsequently, using the patterned photoresist layer 32 as an ion implantation mask, P type ion species such as boron is implanted into the semiconductor substrate 10 through the opening 33, thereby forming P type device isolation diffusion region 36. Thereafter, the patterned photoresist layer 32 is removed. Typically, a thermal drive-in process is performed to activate the dopants previously implanted into the semiconductor substrate 10.
As shown in FIG. 4, a thermal oxidation process is carried out to form field oxide layers 42 and 44 on the surface areas of the semiconductor substrate 10 that are not covered with the mask patterns 20a and 20b. The field oxide layer 42 is formed between the mask pattern 20a and mask pattern 20b, and is contiguous with the underlying N drift region 24. The field oxide layer 44 is formed on the other side of the mask pattern 20b opposite to the field oxide layer 42. The P type device isolation diffusion region 36 is situated directly underneath the field oxide layer 44. In accordance with the prior art method, the P type device isolation diffusion region 36 in the high-voltage device area, which function as a channel stop, are implanted into the substrate 10 prior to the formation of field oxide layers 42 and 44. This is disadvantageous because the dopants in the P type device isolation diffusion region 36 laterally diffuse when taking subsequent high-temperature thermal processes.
As shown in FIG. 5, the mask patterns 20a and 20b are removed. The pad oxide layer 16 is then etched away. As shown in FIG. 6, an oxidation process is performed to grow a gate oxide layer 56 on the exposed semiconductor substrate 10. After the growth of the gate oxide layer 56, a doped polysilicon gate 58 is formed on the gate oxide layer 56 directly above the channel region between the N drift regions 24. The formation of the doped polysilicon gate 58 is known in the art. For example, a chemical vapor deposition process is carried out to deposit a layer of doped polysilicon over the semiconductor substrate 10, followed by lithographic process and dry etching process to pattern the gate.
As shown in FIG. 7, a patterned photoresist layer 72 is formed on the semiconductor substrate 10. The patterned photoresist layer 72 has an opening 73 that exposes the source/drain regions of the high-voltage MOS device. An ion implantation process is performed to implant N type ion species such as phosphorus or arsenic into the N wells 14, thereby forming N+ source/drain region 74. Finally, the photoresist layer 72 is removed.
The above-described prior art method has several drawbacks. First, according to the prior art method, the photoresist layer 32 and an additional photo mask for defining the strip opening 33 are necessary for the implantation of the P type device isolation region 36. Therefore, the cost is high. Second, the P type device isolation region 36 is formed prior to the formation of the field oxide layers 42 and 44, resulting in lateral diffusion of the P type device isolation region 36. The lateral diffusion of the P type device isolation region 36 changes the junction profile of the device isolation diffusion and decreases the doping concentration of the device isolation region 36, thus prohibits the use of poly field device or even M−1 field device at circuit design stage. Further, the lateral diffusion also hinders the shrinkage of the high-voltage MOS device.